Sunday -- Monday
September 18, 2011 (Sunday) |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 1 - Mixed-signal DFT and BIST: Trends, Principles, and Solutions
Presenter: S. Sunter |
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We analyze trends in IC processes and design, and implications for test, then look at trends in testing, such as multi-site and the dominance of MS in test time/effort for SoCs. Next, we discuss trends in standardized DFT, including IEEE 1149.1, .4, .6, .8, and 1687. The trend analysis concludes with a review of DFT techniques, including fault simulation and BIST. Addressed circuits include PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, random analog, and RF. Next, seven essential principles of practical analog BIST are presented. Lastly, we search for the most-practical DFT and BIST techniques, ranging from the basic but limited analog bus, to oversampling and undersampling methods that greatly extend range. Examples and case studies are included. Attendees will gain a clear picture of where they are keeping up with industry, why analog BIST always seems to be a future solution, and how to make parametric DFT, diagnosis, and testing systematic. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 2 - High-Quality and Low-Cost Delay Testing for VDSM Designs: Challenges and Solutions
Presenters: M. Tehranipoor, K. Chakrabarty, J. Rearick |
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As technology scales to 32 nm and functional frequency and density continue to rise, many factors and parameters have shown significant impact on design and test of chips. Test engineers must now deal with many new challenges such as IR-drop and power-supply noise (PSN) effects on chip performance, signal integrity and crosstalk effects on path delay, high test pattern volume, low fault/defect coverage, small delay defect test pattern generation and fault simulation, process variation effects, high cost of test implementation and application, and unmodeled faults. This tutorial provides practice-oriented solutions to the above challenges. The tutorial is designed to provide design and test engineers with in-depth knowledge on high-quality delay test generation for reduced escape and increased in-field reliability. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 3 - Bridge to Moore—IEEE Standards Provide Access to Debug, Validation and Test of Ever More Complex ICs—On ATE, on Board, in System
Presenters: A. Ley, A. Crouch |
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Modern chips have a wealth of embedded content and are becoming more complex in architecture with SOCs being made up of multiple cores and with multiple-TAP configurations; and known-good-die being stacked into SIPs and POPs. The need for access to embedded instruments for debug, validation, test and yield analysis on various occasions during a chip’s life-cycle are driving the industry toward “standard” solutions instead of collections of ad hoc access mechanisms. These solutions include IEEE 1149.1, 1500, 1149.7 and P1687, which provide for, respectively, the original standard test access port (TAP), embedded- core test, the new reduced-pin and enhanced-functionality TAP, and access and control of instrumentation. This tutorial will familiarize the student with these IEEE standards and draft standards, will present the drivers for adoption and use of the standards, will show examples of architectures and usage, and will evaluate pros and cons associated with implementation and use. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 4 - Power-Aware Testing and Test Strategies for Low Power Devices
Presenters: P. Girard, N. Nicolici,
X. Wen |
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Managing the power consumption of circuits and systems is now considered as one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This tutorial provides knowledge in this area. It is organized into three main parts. The first one gives necessary background and discusses issues arising from excessive power dissipation during test application. The second part provides comprehensive knowledge of structural and algorithmic solutions that can be used to alleviate such problems. The last part surveys low power design techniques and shows how these low power devices can be tested safely without affecting yield and reliability. EDA solutions for considering power during test and design-for-test are also discussed in the last part of the tutorial. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 5 - The Convergence and Inter-relationship of Yield, Design for Manufacturability and Test
Presenters: S. Venkataraman, R. Aitken |
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The tutorial goal is to show how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we conventionally think of as test. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced to 90 nm micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. The basics of yield and what fabs do to improve defectivity and manage yield are described. DFM techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield are discussed. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered. This tutorial will provide background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs. |
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September 19, 2011 (Monday) |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 6 - Practices in Analog, Mixed-Signal and RF Testing
Presenters: S. Abdennadher, S. Shaikh |
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The objective of this course is to present existing industry ATE solutions and the alternative solutions to ATE testing for mixed-signal and RF SoCs. These techniques greatly rely upon DFT and BIST structures. Tutorial presents the basic concepts in analog and RF measurements (eye diagram, jitter, gain, power compression, harmonics, noise figure, phase noise, BER, EVM, etc.). Several industrial examples of production testing of mixed-signal and RF devices, such as, SERDES transceivers, PHYs, PMDs, and RF transceivers are also presented. The block-DFT solutions are presented for PLLs, delta-sigma converters, equalizers, filters, mixers, AGC, LNAs, DACs and ADCs. The testing of high speed IO interfaces, such as, PCI-Express, and XAUI, etc, and the new design trends in RF systems such as MIMO and SiP based systems and their testability are also presented in this tutorial. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 7 - Delay Test: Concepts, Theory and Recent Trends
Presenters: S. Natarajan, A. Sinha |
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This is an advanced tutorial on validating and testing integrated circuits for speed failures. It covers fundamental concepts, research ideas and industry practices in delay defect and performance testing of nanometer designs. The intended audience is a combination of semiconductor industry practitioners, EDA technologists, and researchers in digital test. The tutorial starts with a discussion on defects and design marginalities that induce circuits to fail at its rated speed while passing at lower speeds, followed by fault models and fault sensitization conditions. It next discusses test generation, fault simulation and diagnosis algorithms. Design-for-test techniques to apply delay tests, metrics to measure delay test quality, and techniques to improve delay test quality and reduce yield loss are then addressed. Application of delay test techniques in post-silicon validation, defect screening, speed binning and field aging are discussed using industry case studies. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 8 - Demystifying Board-Level Test and Diagnosis
Presenters: K. Chakrabarty, Z. Conroy, W. Eklow |
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The gap between working silicon and a working board/system is becoming more significant and problematic as technology scales and complexity grows. The result of this increasing gap is failures at the board and system level that cannot be duplicated at the component level. These failures are most often referred to as “NTFs” (No Trouble Founds). The result of these NTFs can range from higher manufacturing costs and inventories to failure to get the product out of the door. The problem will only get worse as technology scales and will be compounded as new packaging techniques (SiP, SoC, 3D) extend and expand Moore’s law. This is a problem that must be solved, yet, little effort has been applied up to this point. This tutorial will provide a detailed background on the nature of this problem and will provide DFT and test solutions at both the component and board/system level. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 9 - Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices
Presenter: S. Ravi, R. Kapur,
M. Tehranipoor
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The push for portable, battery-operated, and “cool-and-green” electronics has elevated power consumption as the defining metric of integrated circuit (IC) design. Testing ICs built for such applications requires judicious consideration of test power implications on various aspects of the design cycle (e.g., packaging and power grid design), test engineering (multi-site ATE power supply limitations and board design), power- aware test planning (DFT and ATPG), and developing the enabling EDA tool infrastructure (SW for estimation, reduction and low-power test generation). Furthermore, with power optimization and power management techniques becoming “de-facto” in almost all emerging 45nm and lower chips, systematic testing of these structures and the device in the presence of these structures becomes mandatory. This tutorial is intended to provide an in-depth and up-to-date understanding of low-power IC testing covering (a) dimensions of power-aware testing, (b) techniques for estimation and reduction of test power consumption and (c) test of power managed designs. Case-studies illustrating industrial design deployment practices and existing EDA vendor support will be outlined to illustrate capabilities and gaps in the state-of-the-art. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 10 - Statistical Adaptive Test Methods Targeting "Zero Defect" IC Quality and Reliability
Presenters: A. Singh |
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Integrated circuits have traditionally all been tested identically in the manufacturing flow with little sharing of test results between the different test insertions. However, as the detection of subtle manufacturing flaws becomes ever more challenging and expensive in aggressively scaled nanometer technologies, innovative new statistical screening methods are being developed that attempt to improve test effectiveness and optimize test costs by subjecting “suspect” parts to more extensive testing, and also adaptively bring in additional tests that target the suspected failure mode. The idea is analogous to selective security screening approaches applied at airports. Such statistical methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers, and those that exploit the correlation in the variation of process and performance parameters on wafers. This tutorial presents test methodologies that span both these categories, and illustrates their effectiveness with results from a number of recently published experimental studies on production digital and analog circuits from IBM, Intel and LSI Logic, Analog Devices and NXP Semiconductor. Commercial tools offered by a number of new companies that have emerged in the "Adaptive Test" space will also be discussed. Broadly, these aim provide to support for the sharing and leveraging of results from the different tests in the test flow for effective test adaptation and optimization. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 11 - The Economics of Test and Testability
Presenters: S. Davidson, H. Colby, L. Ungar |
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Test economics provides a way of quantifying the costs and benefits of test, and helps a test engineer choose an effective test strategy. Classical microeconomics is far more sophisticated than what is found in test economics papers. Recent work in behavioral economics, known to the public through bestsellers such as “Freakonomics” and "Predictably Irrational," has shown that classical assumptions about the behavior of economic actors are wrong. This tutorial will summarize existing work in test economics, provide background on microeconomic and behavioral economics concepts that are of interest to test and DFT engineers, and will show their applicability to test. The student will emerge with the ability to do traditional cost and benefit modeling, and with a deeper understanding of the economic principles that affect the cost and benefits of test. The researcher will emerge with the tools to make a much better case for the benefits of proposed research. |
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| 8:30 AM
- 4:30 PM |
TUTORIAL 12 - Testing Memories in the Nano-Era: Fault Models, Test Algorithms, Industrial Results, BIST and BISR
Presenters: S. Hamdioui, A.J. Van de Goor, S. Gregor |
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The objective is to provide attendees with an overview of fault modeling, test design, BIST and BISR for memory devices in the nano-era. Traditional fault modeling and recent development in fault models for current and future technologies are covered. Systematic methods are presented for designing and optimizing tests, supported by industrial results from different companies (e.g. Intel, ST) and for different technology nodes (e.g., 0.13um, 65nm). Impact of algorithmic (e.g., data-background) and non-algorithmic (e.g. voltage) stresses is explored in order to get better insight in the test effectiveness. Novel BIST architectures are covered; special attention is given to the optimization of address generator designs as they typically consume considerable BIST area overhead. BISR and redundancy analysis are also discussed. Moreover, CPU based memory test – which is in some applications the only resource to perform at least the Power-On tests- is addressed. Finally, future challenges in memory testing are highlighted. |
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In addition to the regular tutorials, TTTC/TTEP is offering at ITC 2011 a Test Clinic, particularly geared towards newcomers to the area of test, such as new test engineers and students pursuing graduate studies in test. Its key objective is to offer a broad yet comprehensive review of basic test topics in an accessible way to the lay audience. This year’s topic will be Logic and Memory Testing for SOCs.
The Test Clinic will be a full-day event, which will be held on Monday, September 19th. Upon its completion, an official recognition in the form of an IEEE TTTC Test Technology Certificate will be presented to each participant.
For further information regarding TTEP, please visit http://tab.computer.org/tttc/teg/ttep/ The Test Clinic requires a separate registration fee (see ITC registration form or www.itctestweek.org for further information). Admission for on-site registrants is subject to availability.
Test Clinic attendees receive study material, breakfast, lunch, and coffee breaks. The study material includes a hardcopy of the presentation and bibliographical material. Test Clinic registration, coffee and pastry are available at 7:00 a.m. on Monday.
| 8:30 AM
- 4:30 PM |
TEST CLINIC Logic and Memory Testing for SOCs
Presenters: A. Cron, Y. Zorian |
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Testability is a fundamental requirement for today’s systems-on-chip. These integrated circuits are typically designed based on intellectual property (IP) block integration to make the best use of millions of gates available. Logic and memory IP blocks require adequate fault detection, silicon debug and yield optimization. All of which are based on testability infrastructure build into the systems-on-chip. This tutorial presents the fundamental knowledge base that any designer or testability engineer must have in order to fulfill the current industrial best practices for design-for-testability. The tutorial discusses the requirements for block-level test architecting, at-speed design practices, scan compression, memory self-test, debug and repair, test interface standardization efforts such as IEEE Std 1149.1 (JTAG) and IEEE Std. 1500, and integration for system-on-chip level and beyond. Actual industrial experiences will be shared with the audience whenever possible. |
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